Superconducting circuits are one of the leading technologies proposed for quantum computing and cryptography applications that are expected to provide significant enhancements to national security applications where communication signal integrity or computing power are needed. They are operated at temperatures <100 kelvin. Efforts on fabrication of superconducting devices have mostly been confined to university or government research labs, with little published on the mass producing of superconducting devices. Therefore, many of the methods used to fabricate superconducting devices in these laboratories utilize processes or equipment incapable of rapid, consistent fabrication. Recently there has been a movement to mass producing superconducting circuits utilizing similar techniques as those utilized in conventional semiconductor processes.
One well-known semiconductor process is the formation of contacts and conductive lines in a multi-level interconnect stack to couple devices to one another over different layers of an integrated circuit. One such fabrication process for formation of conductive contacts and lines is known as a dual damascene process. Current dual damascene processes center around copper (Cu) interconnects for sub 130 nanometer (nm) integrated circuits (ICs). There is no known current process of filling a dual damascene structure with a superconducting metal using semiconductor deposition processes.